Numerous applications involve heat-treating a workpiece. For example, in the manufacture of semiconductor chips such as microprocessors and other computer chips, a semiconductor wafer such as a silicon wafer is subjected to an ion implantation process, which introduces impurity atoms or dopants into a surface region of a device side of the wafer. The ion implantation process damages the crystal lattice structure of the surface region of the wafer, and leaves the implanted dopant atoms in interstitial sites where they are electrically inactive. In order to move the dopant atoms into substitutional sites in the lattice to render them electrically active, and to repair the damage to the crystal lattice structure that occurs during ion implantation, it is necessary to anneal the surface region of the device side of the wafer by heating it to a high temperature.
However, the high temperatures required to anneal the device side also tend to produce undesirable effects using existing technologies. For example, diffusion of the dopant atoms deeper into the silicon wafer tends to occur at much higher rates at high temperatures, with most of the diffusion occurring within close proximity to the high annealing temperature required to activate the dopants. Decades ago, diffusion was not as significant a barrier, and the relatively large and deep device sizes prevailing at those times could be manufactured by simply heating the entire wafer isothermally to an annealing temperature and then holding it at the annealing temperature for a relatively long time, such as minutes or even hours, for example.
However, in view of steadily increasing demand for greater performance and smaller device sizes, it is now necessary to produce increasingly shallow and abruptly defined junctions. As a result, diffusion depths that would have been considered negligible in the past or are even tolerable today will no longer be tolerable in the next few years or thereafter.
In light of the above difficulties, commonly owned U.S. Pat. Nos. 6,594,446, 6,941,063 and 6,963,692 (which are hereby incorporated herein by reference) disclose various methods of annealing a semiconductor wafer, such as a flash-assisted rapid thermal processing (fRTP™) cycle, for example. An example of an fRTP™ cycle may involve pre-heating the entire wafer to an intermediate temperature at a ramp rate slower than the thermal conduction rate through the wafer, then heating the device side of the wafer at a rate much faster than the thermal conduction rate, which may be achieved by exposing the device side to an irradiance flash. As an illustrative example, the wafer may be pre-heated to an intermediate temperature such as 600° C. for example, by irradiating the substrate side with an arc lamp to heat the entire wafer at a rate such as 150° C. per second, for example. The device side may then be exposed to a high-intensity flash from a flash lamp, such as a one-millisecond flash, to heat only the device side to an annealing temperature such as 1300° C., for example. Due to the rapid heating rate of the device side during the flash (in excess of 105° C./s), the bulk of the wafer remains at the intermediate temperature, and acts as a heat sink to then cool the device side following the flash. Such a process may achieve the desired annealing temperature while at the same time advantageously minimizing dwell time above the intermediate temperature, thereby controlling dopant diffusion. Adjusting the intermediate temperature can vary the amount of diffusion, while changing the peak temperature can control activation, for example.
Commonly owned U.S. Pat. Nos. 7,445,382 and 7,616,872 and U.S. Patent Application Publication No. US 2007/0069161 (which are hereby incorporated herein by reference) disclose various improvements to such processes, including (among other things) real-time temperature measurement of the device side during an initial portion of the irradiance flash, and real-time feedback control of the remaining portion of the irradiance flash based on the measured temperatures.